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Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.

By: Contributor(s): Material type: TextTextSeries: Frontiers in electronic testing ; 25.Publication details: Boston : Kluwer Academic Publishers, 2003.Description: xiv, 216 p. : illSubject(s): Genre/Form: DDC classification:
  • 621.39/5 22
LOC classification:
  • TK7874.75 .R33 2003
Online resources:
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Includes bibliographical references and index.

Electronic reproduction. Ann Arbor, MI : ProQuest, 2015. Available via World Wide Web. Access may be limited to ProQuest affiliated libraries.

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